Dear Author and Colleague, The 2002 International HDL Conference and Exhibition had many great memories. This conference was attended by over 600 attendees, 18 leading EDA companies exhibited, Raul Camposano with Synopsys, Inc. outlined future challenges to ensure design tools keep up with the demands of Moore's Law at the Tuesday Luncheon Keynote. Attendees overflowed the meeting rooms for two important panel discussions including a session on Verification, popular enough to help change the focus of the conference for 2003 and a session moderated by John Cooley boasting an all-cast of EDA innovators. The annual "Who wants to be a Multi-Million Gate Designer", tested the mettle of a few of our fellow engineers. 2003 will be another exciting year!! For our 12th anniversary session, HDLCon has changed its name to Design and Verification Conference and Exhibition, or DVCon. This new name is both necessary and appropriate. It expands the scope of the conference to include verification languages, as well as hardware description languages and software implementations. It is now a more comprehensive forum to fully explore language solutions to both implement and verify hardware virtual prototypes. With this more complete viewpoint, design engineers, verification engineers, EDA professionals, university researchers, and industry pundits assemble to exchange ideas. The new languages, concepts, papers, panels, tutorials and vendor exhibits - all representing hardware/software design and verification will provide you with an exciting environment for your interaction and your participation. We are happy to announce that DVCon will be held February 24-26, 2003 at the DoubleTree Hotel in San Jose, California. DVCon 2003 is now open for proposals for technical papers, tutorials and panels! We encourage you to contribute your experiences with using hardware design and verification languages, and to participate in the valuable exchange of ideas. The conference will included the following types of presentations: o Technical papers using Hardware Description Languages (HDLs) o Technical papers using Hardware Verification Languages (HVLs) o In-depth tutorials on design and verification techniques o Educational panels on trends in design and verification This will provide you with the opportunity to gain industry-wide recognition and benefit from exchanging information with your papers. All paper presenters, tutorial presenters, and panel moderators will receive complimentary full conference registration. (approximately a $450 value) Details on submitting a paper, tutorial or panel proposal, along with suggested topics, can be found on the Design and Verification Conference web page, at http://www.dvcon.org/dvccfp.pdf The deadline to submit a proposal is Tuesday, October 1, 2002! Please forward this e-mail your fellow engineers who may be interested in participating or attending the conference. We apologize if you should happen to receive multiple copies of this message. Sincerely, Stuart Sutherland Frank Weiler Program Chair General Chair NEW WEBSITE: http://www.dvcon.org/ ********************************************************************** This is the list for the Accellera Member Announcements. You have been subscribed to this list if you have either requested Accellera membership or attended a Accellera sponsored conference. This list is used to send periodic announcements on upcoming events and other useful information. If you would like to remove yourself from this list, please click: http://mpassociates.post.intellimedia.com/UM/U.asp?B1031.32759.91.10274 and you will be removed immediately! Thank you!